1. Field of the Invention
The present invention relates generally to field effect transistors (FETs). More specifically, the present invention relates to an FET in which source and drain extensions do not overlap the gate electrode. This structure lowers the overlap capacitance, thereby allowing high speed operation at subthreshold voltages.
2. Description of the Prior Art
Field effect transistors (FETs) are commonly used in digital electronics and low power electronics. Presently, power dissipation in FET devices is an important factor limiting the reduction in FET size and increases in device density. As FETs are made smaller and packed closer, the power density of an electronic chip increases rapidly, thereby creating excessive heat and operating temperatures destructive to the chip.
One possible solution to the power dissipation problem is to reduce the operating voltage to levels below what is known as the transistor “threshold” voltage, Vt. FIG. 1 shows a plot illustrating the threshold voltage for a typical conventional FET device. The threshold voltage is the voltage at which the source-drain current transitions from an exponential dependence on gate voltage to a linear or quadratic dependence on gate voltage. For typical FET devices used in microprocessors, the threshold voltage is about 0.2 volts. Conventional FET microprocessor circuits operate at voltages far in excess of the threshold voltage, for example at about 1.2 volts or 5–6 times the threshold voltage. Operating at voltages above threshold provides the substantial advantage of increasing the switching speed of the FET device.
However, operating at relatively high voltages increases the power dissipation of the FET, thereby limiting the device density on a chip. It is well known that power dissipation can be greatly diminished by operating at voltages below the threshold voltage. Operating in the “subthreshold” regime would thereby allow for greater device density and parallelism (e.g. parallelism at the circuit design level). Unfortunately, operation in the subthreshold regime reduces the switching speed of the FET. However, it has been discovered that the reduction in switching speed could be more than offset by the allowed increases in device density. In other words, it is possible that the increase in device density and parallelism will more than compensate for the reduced switching speed so that a net increase in processing power is achievable with a subthreshold circuit.
Therefore, subthreshold operation offers a potential solution to the power dissipation problem of conventional processors. Subthreshold FET processors do not guarantee boosts in processing power, however, because the reduction in switching speed at subthreshold voltages can be large.
FET switching speed is adversely affected by the electrical capacitance (“overlap capacitance”) between the gate electrode and the source and drain electrodes.
It would be an advance in the art to provide an FET device having reduced overlap capacitance so that the FET would have greater switching speed in the subthreshold regime. Such an FET could allow subthreshold processor chips to have greater processing power compared to conventional above-threshold processors, and thereby provide a solution to the power dissipation problem that currently limits conventional processors.